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frequency divi d ers & detectors - s m t 1 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper functional diagram i ntegrated frequency s weeper - linear, c oherent s weeps - 2-way, 1-way, & u ser defned s weep modes - automatic or t riggered - programmable s eed - s p i & e xternal t riggering 5-gp io s, can be used for e xternal d s m c ycle s lip prevention s upport with pfd c hip (hm c 984lp4 e ) differential vco i nput & divider o utput programmable o utput c urrent c ontrol: -5 ma to 17.5 ma o pen c ollector o utput driver 32 pin, 5 x 5 mm, lp5 package typical applications t he d c - 7 ghz f r a ction al- n d ivi d er is suitable for: ? t est e quipment ? portable i nstruments ? high performance fractional- n frequency s ynthe - sizers with u ltra low s purious ? s tand-alone divider and/or delta- s igma modulator general description d c - 7 ghz f r a ction al- n d ivi d er is a fractional frequency divider targeted for fractional- n frequency synthesis, and stand-alone low noise frequency divider applications that require exceptional spurious performance. although the d c - 7 ghz f r a ction al- n d ivi d er can work with any vco and/or compatible phase detector, best performance and features will be achieved when paired with the companion part, the hm c 984lp4 e. fabricated in s ige bi c m os process, the d c - 7 ghz f r a ction al- n d ivi d er features a 48-bit delta s igma fractional modulator (d s m) with programmable phase accumulator size, enabling precise control of frequency step size and resolution. i ntegrated d s m can generate frequencies with nearly 0 hz frequency error. t he d s m also includes a built-in programmable frequency sweep capability, with various automatic and user defned sweep modes and triggering options, including hardware trigger pin, or s p i trigger with optional delayed trigger. d c - 7 ghz f r a ction al- n d ivi d er is a versatile part capable of various confgurations. i t has 5 general purpose i / o s (gp io s). d s m outputs are made available from the gp io port, enabling the d c - 7 ghz f r a ction al- n d ivi d er to import and/ or export d s m sequences for various confguration options. d c - 7 ghz f r a ction al- n d ivi d er divider outputs are differential, open collector with programmable current to accommodate different off-chip loads. features wideband: d c - 7 ghz i nput -20-bit frequency divider low n oise: -160 dbc/hz low s purious: largest s purious - 95 dbc 48-bit 100 mhz delta- s igma modulator (d s m) - c onfgurable d s m s ize - programmable s eed - phase s tep features (continued) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 2 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper table 1. electrical specifcations t a = +25 c , a v dd, vcc p s , vcc hf, v ddm, d v dd = 3 v 10%; v ppb u f = 5 v 10%; g n d = 0 v parameter c onditions min. t yp. max. u nits rf input characteristics r f i nput frequency range dc 7 ghz r f i nput s ensitivity -15 -10 0 dbm r f i nput c apacitance e xternal match r ecommended 3 pf divider r ange (20-bit) i nteger mode 32 1,048,575 fractional mode 36 1,048,571 divider output characteristics o utput buffer c urrent programmable in 2.5 ma s teps 5 12.5 17. 5 ma o utput v oltage s wing s ingle- e nded, v pullup = 5 v 0.75 1 2 v o utput frequency r ange i nteger mode fractional mode mode a and mode b dc dc 150 125 mhz phase n oise 50 mhz pfd, 6 ghz i nput, i nteger mode -160 dbc/hz fractional s purious largest observed at 10 khz fractional o ffset from i nteger boundary -95 -85 dbc logic inputs i nput high v oltage ( vi h) dv dd-0.4 v i nput low v oltage ( vi l) 0.4 v logic outputs o utput high v oltage ( vo h) dv dd-0.4 v o utput low v oltage ( vo l) 0.4 v d c load 1.5 ma s erial port c lock frequency main s p i and a u x s p i 30 mhz power supplies a v dd, vcc p s , vcc hf analog s upplies. a v dd should be equal to d v dd. 2.7 3 3.3 v v ppb u f o utput buffer s upply. 4.5 5 5.5 v v ddm, d v dd digital s upplies 2.7 3 3.3 v current consumption i dd - t otal c urrent c onsumption i nteger mode / fractional mode (50 mhz divider o utput) 104 / 122 ma i - a v dd (a v dd c urrent, 3 v ) i nteger mode / fractional mode 5 / 5 ma i - vcc p s ( vcc p s c urrent, 3 v ) i nteger mode / fractional mode 79 / 79 ma i - vcc hf ( vcc hf c urrent, 3 v ) i nteger mode / fractional mode 8 / 8 ma i - v ddm ( v ddm c urrent, 3 v ) i nteger mode / fractional mode 11 / 11 ma i - d v dd ( t otal d v dd c urrent, 3 v ) i nteger mode / fractional mode 1 / 19 ma i - v ppb u f ( t otal v ppb u f c urrent, 5 v ) 5 ua for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 3 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper figure 1. rf input sensitivity [1] figure 3. output phase noise with 6 ghz input in integer mode [3] figure 2. output phase noise, 6 ghz input frequency [2] figure 5. time domain 18 mhz output, 6.5 ghz input [4] figure 4. time domain 10 mhz output, 6.5 ghz input [4] figure 6. time domain 35 mhz output, 6.5 ghz input [4] -200 -180 -160 -140 -120 -100 -80 -60 10 2 10 3 10 4 10 5 10 6 10 7 10 8 offset frequency (hz) phase noise (dbc/hz) rf input signal phase noise 100 mhz output frequency integer mode 100 mhz output frequency frac mode b 100 mhz output frequency frac mode a -80 -60 -40 -20 0 20 40 0 2000 4000 6000 8000 10000 +27 c -40 c +85 c rf input frequency (mhz) rf input power (dbm) recommended operating range maximum input power limit minimum input power limit -200 -180 -160 -140 -120 -100 -80 -60 10 2 10 3 10 4 10 5 10 6 10 7 10 8 offset frequency (hz) phase noise (dbc/hz) rf input signal phase noise calculated phase noise 50 mhz output frequency 100 mhz output frequency 142 mhz output frequency 4 4.5 5 5.5 0 50 100 150 200 250 300 350 time (ns) outout voltage (v) divckpfdp pin output divckpfdn pin output 4 4.5 5 5.5 0 50 100 150 200 time (ns) output voltage (v) divckpfdp pin output divckpfdn pin output 4 4.5 5 5.5 0 20 40 60 80 100 time (ns) output voltage (v) divckpfdp pin output divckpfdn pin output [1] t he maximum and minimum levels indicate operational limits of the d c - 7 ghz f r a ction al- n d ivi d er . performance may degrade with input power greater than 0 dbm for frequencies higher than 6500 mhz. [2] due to delta s igma modulation in fractional mode, the output phase noise peaks at frequency offset of fout/2 from the output. agilent mxg n 5182a used as a signal source. [3] r ohde & s chwarz s mb v 100a used as a signal source. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 4 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper figure 7. time domain 124 mhz output, 6.5 ghz input [5] figure 8. time domain 66 mhz output, 6.5 ghz input [5] figure 9. time domain 61 mhz output, 6.5 ghz input [5] figure 10. time domain 66 mhz output, 6.5 ghz input [5] figure 11. 10 mhz output swing vs buffer current [6] figure 12. 50 mhz output swing vs buffer current [6] 4 4.5 5 5.5 0 5 10 15 20 25 30 time (ns) output voltage (v) divckpfdp pin output divckpfdn pin output 4 4.5 5 5.5 0 10 20 30 40 50 time (ns) output voltage (v) divckpfdp pin output divckpfdn pin output 4 4.5 5 5.5 0 10 20 30 40 50 time (ns) output voltage (v) divckpfdp pin output divckpfdn pin output 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 12 13 14 15 16 17 18 -40 c +27 c +85 c output buffer current (ma) single-ended output swing (vpp) 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 12 13 14 15 16 17 18 -40 c +27 c +85 c output buffer current (ma) single-ended output swing (vpp) 4 4.5 5 5.5 0 10 20 30 40 50 time (ns) output voltage (v) divckpfdp pin output divckpfdn pin output [4] measured with 50 impedance per line, integer mode, 15 ma o utput buffer c urrent ( r eg 0fh [4:2]) selected [5] measured with 50 impedance per line, integer mode, 15 ma o utput buffer c urrent ( r eg 0fh [4:2]) selected for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 5 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper figure 13. 100 mhz output swing vs buffer current [7] figure 14. input return loss figure 15. two way frequency sweep, 50 mhz pfd [8] figure 16. one way frequency sweep, 10 mhz pfd and 10 hz external trigger [8] figure 17. pll cycle slip prevention, 100 mhz pfd [8] figure 18. pll cycle slip prevention, 50 mhz pfd [8] 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 12 13 14 15 16 17 18 -40 c +27 c +85 c output buffer current (ma) single-ended output swing (vpp) -20 -15 -10 -5 0 0 2000 4000 6000 8000 frequency (mhz) return loss (db) 6400 6500 6600 6700 6800 6900 7000 0 5 10 15 20 frequency (mhz) time (ms) 6400 6500 6600 6700 6800 6900 7000 0 200 400 600 800 1000 frequency (mhz) time (ms) 6700 6750 6800 6850 6900 6950 7000 7050 0 50 100 150 200 250 300 time (us) pll output frequency (mhz) cycle slip disabled csp enabled reg0eh[18:15] = 8h csp enabled reg0eh[18:15] = 1h 6700 6750 6800 6850 6900 6950 7000 7050 0 50 100 150 200 250 300 time (us) pll output frequency (ghz) cycle slip disabled csp enabled reg0eh[18:15] = fh csp enabled reg0eh[18:15] = 5h [6] measured with 50 impedance per line. buffer current is controled via r eg 0fh [4:2]. [7] measured with 50 impedance per line. buffer current is controled via r eg 0fh [4:2]. [8] measured with hm c 983lp5 e /hm c 984lp4 e chip set as fractional- n synthesizer. c rystal input frequency = 100 mhz, c p current = 2.5 ma, cp offset current = 245 ua, loop flter bandwidth = 87 khz, d s m mode b selected. c ycle s lip prevention (cs p) is disabled in hmc984lp4e by setting r eg 01h [4] = 0. s etting r eg 01h [4] = 1 enables cs p in the two chip pll. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 6 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper table 2. pin descriptions pin n umber function description i nterface s chematic 1, 2, 3 sen b s di sc k main s p i data i nput 4, 5 d1 d0 gp io bit 1 gp io bit 0 6, 7, 8 au x_ sc lk a u x_ sen b au x_ s d o auxiliary s p i c lock o utput auxiliary s p i e nable auxiliary s p i data o utput 9 b i a s e xternal decoupling for analog bias c ircuits 10 av dd 3 v olt power s upply pin for i nternal r eference c ur - rent s ources 11 vcc p s 3 v olt power s upply pin for prescaler 12, 13 vcoin , vcio p n egative pin for prescaler differential i nput, a c - c oupled positive pin for prescaler differential i nput, a c - c oupled 14 vcc hf 3 v olt power s upply pin for prescaler i nput buffer 15 v ppb u f 5 v olt power s upply pin for divider o utput buffer 16 n /c n o c onnect pin for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 7 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper table 2. pin descriptions pin n umber function description i nterface s chematic 17, 18 div c kpfdn, div c kpfdp n egative pin for o pen c ollector divider o utput driver positive pin for o pen c ollector divider o utput driver 19 v ddm 3 v s upply pin for digital s ection of the frequency divider 20, 21, 22 d2, d3, d4 gpio bit 2, gpio bit 3, gpio bit 4 23 re f_ e no gate c ontrol ( o utput) to request tcx o c lock e xport from hmc984lp4e 24, 25, 26 c h i p1, c h i p2, c hi p3 c hip address pin 1, c hip address pin 2, c hip address pin 3 27, 3 0 dv dd 3v power s upply for digital 28, d ns a t, vco s aturation i nput fag from hmc984lp4e chip (continued) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 8 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper table 2. pin descriptions pin n umber function description i nterface s chematic 29 u p s a t r eference s aturation i nput fag from hmc984lp4e chip 31 cen chip e nable 32 s d o main spi data output (continued) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 9 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper outline drawing part n umber package body material lead finish m s l r ating [2] package marking [1] d c - 7 ghz f r a ction al- n d ivi d er r oh s -compliant low s tress i njection molded plastic 100% matte s n m s l1 h983 xxxx [1] 4-digit lot number xxxx [2] max peak refow temperature of 260 c package information table 3. absolute maximum ratings n ominal 3 v s upplies to g nd -0.3 to 3.6 v n ominal 3 v digital s upply to 3 v analog s upply -0.3 to +0.3 v n ominal 5 v s upply to g n d ( v ppb u f) -0.3 to 5.5 v div c kp, div c kn common mode d c vcc p s + 0.5 v min vcoi p, vcoin single e nded a c 50 s ource + 7 dbm vcoi p, vcoin differential a c 50 s ource + 13 dbm digital input v oltage r ange -0.25 to d v dd + 0.5 v minimum digital load 1 k o perating t emperature r ange -40 c to +85 c maximum junction t emperature 125 c s torage t emperature -65 to +125 c e l ectrost a tic sensitive d evice o b serve ha n dl in g p rec a utions t hermal r esistance ( rth) (junction to ground paddle) 40 c /w r efow s oldering peak t emperature t ime at peak t emperature 260 c 40 s es d s ensitivity (hbm) c lass 1b s tresses above those listed under absolute maximum r atings may cause permanent damage to the device. t his is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. e xposure to absolute maximum rating conditions for extended periods may affect device reliability. notes : [1] pa c kag e b o d y ma teri al: l o w stress in j ection m o ld e d pla stic si l ic a a n d si l icon i mp re g n a te d. [2] l e ad a n d g roun d paddl e ma teri al: co pp er all oy . [3] l e ad a n d g roun d paddl e pla tin g: 100% ma tte tin . [4] di m ensions a re in inc h es [m ill i m eters ]. [5] l e ad s pa cin g to l er a nce is non - cu m u la tive . [6] pad b urr l en g t h s hall b e 0.15 mm max. pad b urr h ei gh t s hall b e 0.25 m max. [7] pa c kag e wa r p s hall not e x cee d 0.05 mm [8] all g roun d l e ad s a n d g roun d paddl e m ust b e so ld ere d to p c b r f g roun d. [9] re f er to h ittite appl ic a tion note f or su gg este d p c b la n d pa t tern . for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 10 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper evaluation pcb i tem c ontents part n umber e valuation kit d c - 7 ghz f r a ction al- n d ivi d er and hm c 984lp4 e pll c hipset e valuation p c b us b i nterface board 6 us b a male to us b b female c able c d ro m ( c ontains u ser manual, e valuation p c b s chematic, e valuation s oftware) e k it 01- d c - 7 ghz f r a ction al- n d ivi d er table 4. evaluation order information t he circuit board used in the application should use r f circuit design techniques. s ignal lines should have 50 o hms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown unless mentioned otherwise. a sufficient number of via holes should be used to connect the top and bottom ground planes. t he evaluation circuit board shown is available from hittite upon request. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 11 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper evaluation pcb block diagram for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 12 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper theory of operation t he d c - 7 ghz f r a ction al- n d ivi d er can be used in following confgurations: 1. fractional- n or i nteger mode r f frequency divider or prescaler 2. fractional- n frequency s ynthesizer with an appropriate phase detector and vco primary target application of the d c - 7 ghz f r a ction al- n d ivi d er is to be used in conjunction with the a n d f requency s w ee p er as shown in figure 19 . t ogether these two components form a high performance, low noise, ultra low spurious emissions fractional- n frequency synthesizer. figure 19. typical application of hmc984lp4e with hmc983lp5e to form a frequency synthesizer t he d c - 7 ghz f r a ction al- n d ivi d er consists of the following functional blocks 1. r f i nput buffer 2. 7 ghz frequency prescaler and multi modulus divider 3. 48-bit c onfgurable fractional delta s igma modulator 4. bias c ircuit 5. differential o utput driver 6. frequency s weeper 7. main s erial port i nterface 8. auxiliary s erial port i nterface ( o utput o nly) 9. general purpose digital io 10. power o n r eset c ircuit rf input buffer t he r f input stage provides the path from the external vco to the fractional r f divider. t he r f input path is rated to operate nominally from d c to 7 ghz. t he d c - 7 ghz f r a ction al- n d ivi d er r f input stage is a differential common emitter stage with d c coupling, and is protected by es d diodes as shown in figure 20 . r f input is not matched to 50 ? due to wide input frequency range. at low frequencies, a simple shunt 50 ? resistor can be used external to the package to provide a 50 ? match. for better performance it is recommended to match the r f inputs externally and provide differential drive from the vco . i n most applications the input is used single-ended into either the vcoi p or vcoin pin with the other input connected to ground through a d c blocking capacitor. t he preferred input level for best spectral performance is -10 dbm. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 13 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper figure 20. rf input stage rf path fractional-n divider t he r f input buffer is followed by a high frequency prescaler and a multi modulus divider. t he divider has been designed for the best output phase noise and spurious performance in both fractional and integer mode. t he fractional- n divider can divide input frequencies from 32 to 2 20 -1 (1048575) in integer mode and from 36 to 2 20 -5 (1048571) in fractional- n mode. t he divider output pulse width depends on the r f input period and is adjustable via s p i setting (refer to duty c ycle s etting in register r eg 00h c hip i d, s oft r eset, r ead r egister [14:12]). t he output pulse width recommended setting is 40% to 60% where possible. at low output frequencies it may not be possible to set 50% duty cycle. i n such cases the maximum pulse width setting is recommended. figure 21. divider path divider output buffer t he divider output is differential and the output buffer stage is an open collector amplifer with off-chip pull-up resistors. due to sharp rise and fall times at the divider output, the external path should be designed differentially using r f techniques. when d c - 7 ghz f r a ction al- n d ivi d er and a n d f requency s w ee p er are operating together as a frequency synthesizer, 50 ? pull-up resistors are provided in a n d f requency s w ee p er . v ppb u f pin should be connected to 5 v power supply. t his pin does not sink d c current and is only used to bias the internal es d diodes and to provide an appropriate voltage level for the phase detector chip (a n d f requency s w ee p er ). t he two possible interface confgurations are shown in figure 22 and figure 23 below. t he rising edge of the hm c 983lp5 e divider output div c kpfdp and falling edge of div c kpfdn are conditioned and re- synchronized for best spectral performance. t he alternative edges are not t his means for best spectral performance the hm c 983lp5 e must be used with a pfd, not an analog mixer. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 14 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper figure 22. generic divider output interface figure 23. divider interface with and frequency sweeper chip address pins t he d c - 7 ghz f r a ction al- n d ivi d er has three s p i chip address pins ( s p i address [2:0] = c h i p3, c h i p2, c h i p1), which enable multiple d c - 7 ghz f r a ction al- n d ivi d er devices to use the same s p i bus. s p i chip address bits are read at power up, or every time d c - 7 ghz f r a ction al- n d ivi d er is reset. by default, all three pins are internally pulled to d v dd, thus there is no need to connect the pins to d v dd to set them to logic high. t o assign a 0 to any chip address bit, the corresponding pin should be connected to ground. when used on the same s p i bus together with the companion part (the a n d f requency s w ee p er ), to form a frequency synthesizer, some s p i commands, such as changing the reference division ratio to the a n d f requency s w ee p er may also require an action by the d c - 7 ghz f r a ction al- n d ivi d er . i n order to avoid the necessity to write two separate s p i transfers to implement one command (one to confgure a n d f requency s w ee p er , and the other one to confgure the d c - 7 ghz f r a ction al- n d ivi d er ), it is possible to write the s p i address of the companion part (a n d f requency s w ee p er ) into r eg 09h of the d c - 7 ghz f r a ction al- n d ivi d er . i n such cases, the d c - 7 ghz f r a ction al- n d ivi d er is able to recognize an s p i command to the companion part (the a n d f requency s w ee p er ) that requires its own action, and act accordingly to update its own corresponding for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 15 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper registers. writing d c - 7 ghz f r a ction al- n d ivi d er s own chip address to the companion chip address register r eg 09h will disable this feature. saturation detection input pins dnsat, upsat when the d c - 7 ghz f r a ction al- n d ivi d er is operating with its companion chip the a n d f requency s w ee p er as a frequency synthesizer, it automatically detects large phase errors and tries to tune the vco faster by using its algorithm for cycle-slip prevention ( cs p). t he u p s a t and d ns a t provide indication which frequency is higher ( vco or r eference) from the counterpart phase detector/ c harge pump (the a n d f requency s w ee p er ). t he cs p algorithm manipulates the r f divider and the phase detector at appropriate intervals to lock faster. s ee a n d f requency s w ee p er data sheet for more details. t hese pins should be connected to ground if not used. ref_ eno pin re f_ e no pin is a digital output pin that is used by the d c - 7 ghz f r a ction al- n d ivi d er to request crystal oscillator clock from the phase detector / c harge pump chip (the a n d f requency s w ee p er ). t he crystal oscillator clock is multiplexed on the d c - 7 ghz f r a ction al- n d ivi d er s d ns a t pin. t he internal frequency divider, programmed in r eg 02h, is used to generate the actual reference frequency present at the phase detector. t he imported clock is only used to communicate through the a u x s p i . at all other times, the clock and the local reference dividers are turned off. i n stand-alone applications, if the d c - 7 ghz f r a ction al- n d ivi d er is required to communicate through the auxiliary s p i , the d c - 7 ghz f r a ction al- n d ivi d er will expect to receive the auxiliary s p i clock on d ns a t pin. s etting r eg 04h [15] = 1 keeps the auxiliary s p i clock enabled on the d ns a t pin. multi purpose digital io pins d0, d1, d2, d3, d4 (gpio pins) t he fve general purpose digital input/outputs can be used for various modes of operation as well as test/debugging purposes. gp io pins are enabled by writing r eg 01h [4] = 1 (gp io master enable). s etting r eg 01h [4] = 0 places the gp io pins in tri-state high impedance mode. gp io pins are confgured in r eg 08h [13:0]. all of the pins can confgured to be either inputs or outputs by writing to r eg 08h [13:9]. i n frequency sweep mode, pin d4 can be used as an external trigger pin, by writing r eg 08h [13] = 0. writing to r eg 08h [3:0] selects d c - 7 ghz f r a ction al- n d ivi d er s internal signals to be multiplexed out on the gp io pins, as shown in t able 5 . s ignals include: 1. t he output of the delta- s igma modulator r eg 08h [3:0] = 0010b. 2. gp io test signals r eg 08h [3:0] = 0000b, which outputs data written to r eg 08h [8:4] to test the gp io pins. 3. s weep status fags, when the d c - 7 ghz f r a ction al- n d ivi d er is confgured to be in sweep mode r eg 08h [3:0] = 1000b. table 5. gpio pin assignment and output signals r eg 08h [3:0] dc - 7 ghz fra ction al-n divider gpio pins d4 d3 d2 d1 d0 0000 gpo_test_out[4] gpo_test_out[3] gpo_test_out[2] gpo_test_out[1] gpo_test_out[0] 0001 reserved reserved reserved reserved reserved 0010 d s m_ out [4] d s m_ out [3] d s m_ out [2] d s m_ out [1] d s m_ out [0] 0 011 reserved reserved reserved reserved reserved 0100 reserved reserved reserved reserved reserved 0101 reserved reserved reserved reserved reserved for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 16 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper table 5. gpio pin assignment and output signals r eg 08h [3:0] dc - 7 ghz fra ction al-n divider gpio pins d4 d3 d2 d1 d0 0110 reserved reserved reserved 0 0 0111 reserved reserved reserved reserved reserved 1000 ramp_ready_fag ramp_start_fag ramp_stop_fag ramp_busy_falg reserved 10 01-1111 0 0 0 0 0 fractional mode of operation i n addition to providing simple integer division ratios, the d c - 7 ghz f r a ction al- n d ivi d er has a sophisticated, confgurable 48-bit delta s igma modulator (d s m), that allows fractional division of the input frequency in ultra fne steps. t he d s ms size can be confgured to 16/24/32/48 bits ( r eg 16h [5:0]). d c - 7 ghz f r a ction al- n d ivi d er s auto-seed mode allows coherent frequency sweeps. t he d c - 7 ghz f r a ction al- n d ivi d er with its counterpart (the a n d f requency s w ee p er ), together with an external vco comprise a fully functional fractional- n synthesizer. i n that case, the output frequency of the external vco is given by: int int 2 xtal xtal vco frac frac l ff f n n ff r r = ?+ ? =+ ? (e q 1) when the d c - 7 ghz f r a ction al- n d ivi d er is being used as frequency divider, the output frequency is given by; int 2 vco out frac l f f n n = + (e q 2) where f vco is the vco frequency in hz; f xtal is the crystal oscillator frequency in hz; n int is the integer part of frequency division ratio (set in r eg 05h [19:0]); n frac is the fractional part of frequency division ratio ( n frac [47:18] = r eg 06h [29:0], n frac [17:0] = r eg 07h [17:0]) r is the reference frequency division ratio; l is the size of the d s m accumulators (set in r eg 16h [5:0]) example 1: c alculate the vco frequency with the following parameters; f xtal = 50 mhz; f pfd = 25 mhz n int = 25; n frac = 1; l = 24 where f pfd is the frequency at the phase detector, thus r = 2. according to (e q 1) , the vco frequency with the above parameters will be; for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 17 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper 24 50 50 25 1 2500 1.49 2 22 vco mhz mhz f mhz hz = ? + ?= + ? i f accumulator width (l) is changed to 48-bit, then the frequency resolution will improve and the fractional resolution of the vco frequency will be 88.8178 nano-hz. example 2: s et the vco frequency to 4600.025 mhz using 100 mhz c rystal, r = 2 and l = 16. c ompare if l = 32. for this example the f pfd = 100 mhz/2 = 50 mhz, t he overall division ratio is 4600.025 mhz/50 mhz = 92.0005 t he nearest integer would be 92, thus n int = r eg 05h [19:0] = 92d = 5 c h. for l = 16, n frac = 32.768 or 33d rounded up. t hus n frac = 33d or 21h ( r eg 06h [29:0] = 0, r eg 07h [17:0] = 21h). for l = 32, n frac = 2147483.648 or 2147484d rounded up. t hus n frac = 20 c 49 c h ( r eg 06h [29:0] = 8h, r eg 07h [17:0] = 001100010010011100d). s ince n frac must be an integer, the actual frequencies in the two cases will have an error of + 177.02 hz for l = 16 and only +0.004098 hz for l = 32. phase noise in integer and fractional modes i n a normal integer frequency divider the in-band phase noise is scaled from the input phase noise by 20log10( n ), where n is the divider value. i n hm c 983lp5 e fractional mode, the frequency divider is modulated by the delta s igma modulator to generate output frequencies that are fractional multiple of the input frequency. delta s igma modulator shapes the quantization noise such that quantization noise density has a high pass shape which peaks at fs/2, where fs is the sampling frequency (the divider output frequency in case of hm c 983lp5 e ). i n fractional mode this quantization noise peak appears at an offset frequency of fout/2. i n the pll, this peak is attenuated by the loop flter. however, when the hm c 983lp5 e is used stand-alone in fractional mode its output will exhibit the quantization noise as shown in figure 2 and figure 3 . as a result, it is not possible to achieve the same noise foor in fractional mode as in integer mode without further fltering. cw frequency sweeper t he d c - 7 ghz f r a ction al- n d ivi d er features a built-in frequency sweeper function that supports automatic or externally triggered sweeps. e xternal triggering can be executed via an external trigger pin d4 or the s p i interface. d c - 7 ghz f r a ction al- n d ivi d er sweep function can be confgured to operate in the following modes: ? 2-way sweep mode ? r epeating alternating positive and negative frequency sweep ramps ? frequency increments swept with automatic sequencer ? automatic or triggered ? s ymmetric or asymmetric (the positive ramp can have a different slope from that of the negative ramp) ? 1-way s weep mode ? r epeating one directional frequency sweeps followed by a reset to the starting frequency ? frequency increments swept with automatic sequencer ? t riggered u ser defned sweep mode ? manually programmed user defned sweep patterns ? t riggered ? s ymmetric or asymmetric (the positive ramp can have a different slope from that of the negative ramp) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 18 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper i n all sweep modes, the starting sweep direction can be set to positive (increasing) or negative (decreasing). t he trigger can be applied instantaneously or delayed by a programmable time delay. d c - 7 ghz f r a ction al- n d ivi d er s sweep function is illustrated in figure 24 . t he d c - 7 ghz f r a ction al- n d ivi d er generates a frequency sweep by implementing automatic, or triggered in u ser defned mode, discrete miniature frequency increments in time. a smooth and continuous sweep is then generated, at the output of the vco , after the stepped signal is fltered by the loop flter, as shown in figure 24 . t he stepped sweep approach enables the frequency synthesizer (comprising of d c - 7 ghz f r a ction al- n d ivi d er together with its counterpart, the hm c 984lp4 e ) to be in lock for the entire duration of the sweep. t his approach results in a number of advantages over conventional methods including: ? t he ability to generate a linear sweep. ? t he ability to have phase coherence between different sweep ramps, so that the phase profle of each sweep is identical. ? t he ability to generate user defned sweeps in u ser defned s weep mode. figure 24. dc - 7 ghz fractional-n divider sweep function i t is important to note that the synthesized ramp is subject to normal phase locked loop dynamics. i f the loop bandwidth in use is much wider than the rate of frequency increments then the locking will be fast and the ramp will have a staircase shape. i f the update rate is higher than the loop bandwidth, as is normally the case, the loop will not fully settle before a new frequency step is received. hence the swept output will have a lag and will sweep in a near continuous fashion. i n all sweep modes, ramp_busy fag indicates an active sweep and will stay high between the 1st and nth ramp increment. ramp_busy may be monitored on pin d1 by setting r eg 08h [3:0] = 8h. triggering i n sweep mode, the d c - 7 ghz f r a ction al- n d ivi d er can be triggered via one of two methods ? s p i trigger by setting r eg 0 eh [12]=1. t his triggering method is asynchronous to the reference clock. t o enable s p i trigger write r eg 0 eh [13] = 0. ? or applying an external trigger on pin d4. s etting r eg 0 eh [13] = 1 and r eg 08h [13] = 0h confgures d c - 7 ghz f r a ction al- n d ivi d er s pin d4 as external trigger input. e xternal trigger on pin d4 is triggered on the rising edge of the trigger. gp io master enable ( r eg 01h [4] = 1) is also required. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 19 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper ? e xternal triggering method can be synchronized with the reference clock, by enabling trigger delay ( r eg 0 eh [7] = 1), and programming a trigger delay in r eg 05h [20:0] = number of delayed reference periods. writing r eg 05h [20:0] = 1 for example ensures that the trigger is applied at the instant of the rising edge of the next reference rising edge. t o disable trigger delay write r eg 0 eh [7] = 0. 2-way sweep mode d c - 7 ghz f r a ction al- n d ivi d er s 2-way sweep mode is shown in figure 25 . t he 2-way sweep mode can be automatic or triggered. i n automatic 2-way sweep, the trigger is generated internally based on user defned 2-way sweep mode confguration. i n a triggered 2-way sweep, frequency ramps are triggered either by external pin d4, or s p i trigger. figure 25. dc - 7 ghz fractional-n divider 2-way triggered sweep triggered 1-way sweeps d c - 7 ghz f r a ction al- n d ivi d er s 1-way sweeps is shown in figure 26 . u nlike 2-way sweeps, 1-way sweeps require that the vco hop back to the start frequency after the dwell period. t riggered 1-way sweeps also require a 3rd trigger to start the new sweep. t he 3rd trigger must be timed appropriately to allow the vco to settle after the large frequency hop back to the start frequency. s ubsequent odd numbered triggers will start each sweep and repeat the process. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 20 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper figure 26. dc - 7 ghz fractional-n divider 1-way triggered sweep 1-way sweeps are not recommended in auto-sweep mode since in auto-sweep the new sweep will start immediately after the 2nd trigger, as it does in 2-way mode. user defned sweep mode i n u ser defned s weep mode, the d c - 7 ghz f r a ction al- n d ivi d er is able to generate various user-defned sweep patterns by adjusting the time interval between adjacent frequency increments, which are executed by trigger events. d c - 7 ghz f r a ction al- n d ivi d er s u ser defned s weep mode is shown in figure 27 . i n this mode, an external trigger is required for each frequency increment of the sweep. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 21 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper figure 27. dc - 7 ghz fractional-n divider user defned sweep u ser defned sweep can function in both 1-way or 2-way sweep mode. i n 1-way sweep mode, the n+1 trigger will cause the ramp to jump to the start frequency, and the n+2 trigger will restart the 1-way sweep. detailed sweeper confguration r ecommended procedure for confguring d c - 7 ghz f r a ction al- n d ivi d er sweeper in all three modes is shown in t able 6 . for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 22 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper table 6. dc - 7 ghz fractional-n divider sweeper confguration sequence steps description sweeper modes 2-way sweep mode user defned sweep mode 1-way sweep mode 1 lock to start frequency (f o ) ? set the integer ( r eg 05h ) and fractional ( r eg 06h and r eg 07h ) divider values. ? o ptionally, if required the seed ( r eg 0ah and r eg 0bh ) can also be programmed 2 place the d s m in sweep mode ? write r eg 0 e h [11] = 1 3 c onfgure sweep mode ? disable single step ramp mode ( r eg 0 eh [24] = 0), so that each frequency increment will be incremented automatically ? e nable 2-way sweep mode (disable 1-way sweep mode ( r eg 0 e h [25] = 0)) ? t o place the d c - 7 ghz f r a ction al- n d ivi d er in automatic sweep mode write r eg 0 e h [2:3] = 11. t o place the d c - 7 ghz f r a ction al- n d ivi d er in triggered mode write r eg 0 e h [2:3] = 00. ? e nable the single step ramp mode ( r eg 0 e h [24] = 1), so that each frequency increment will require a trigger ? e nable 1-way sweep mode ( r eg 0 eh [25] = 1), or enable 2-way sweep mode ( r eg 0 e h [25] = 1) ? t o place the d c - 7 ghz f r a ction al- n d ivi d er in triggered mode write r eg 0 e h [2:3] = 00. automatic u ser defned s weep mode is not supported. ? disable single step ramp mode ( r eg 0 eh [24] = 0), so that each frequency increment will be incremented automatically ? e nable 1-way sweep mode ( r eg 0 eh [25] = 1) ? t o place the d c - 7 ghz f r a ction al- n d ivi d er in triggered mode write r eg 0 e h [2:3] = 00. automatic 1-way s weep mode is not supported. 4 program s weep direction ? r eg 0 e h [26] = 1 begin sweep in positive direction, r eg 0 e h [26] = 0 begin sweep in negative direction 5 c onfgure symmetrical/ asymmetrical sweep ? program ramp mode (symmetrical - r eg 0 e h [22] = 1, asymmetrical - r eg 0 eh [22] = 0). i f symmetrical ramp mode is selected ( r eg 0 e h [22] = 1), only u p sweep parameters will be used for both positive and negative sweeps, and hence down sweep parameters dont need to be programmed. i n symmetrical ramp mode the positive and negative ramps are identical and opposite in direction. ? program r eg 0 e h [22] = 1. asymmetrical sweep is not defned in 1-way s weep mode 6 program u p s weep parameters ? s et dwell time(dwell time[47:0] = r eg 10h [29:0], dwell time[17:0] = r eg 11h [17:0]) ? s et step size (step size[47:18] = r eg 12h [29:0], step size[17:0] = r eg 13h [17:0]) ? s et the number of steps in a sweep (number of steps[47:18] = r eg 14h [29:0], number of steps[17:0] = r eg 15h [17:0]) 7 program down s weep parameters ( o nly if using asymmetrical sweep (if r eg 0 eh [22] = 0) in s tep 5) ? s et dwell time (dwell time[47:0] = r eg 06h [47:18], dwell time[17:0] = r eg 07h [17:0]) ? s et step size (step size[47:18] = r eg 19h [29:0], step size[17:0] = r eg 1ah [17:0]) ? s et the number of steps in a sweep (number of steps[47:18] = r eg 0 ch [29:0], number of steps[17:0] = r eg 0dh [17:0]) ? asymmetrical sweep is not defned in 1-way s weep mode 8 c onfgure and apply trigger ? t o use s p i trigger write r eg 0 e h [13] = 0 to select s p i trigger. s p i trigger is executed by writing to r eg 0 e h [12] = 1. ? t o use external trigger on pin d4 write r eg 0 e h [13] = 1 to confgure pin d4 as an external trigger. write r eg 08h [13] = 0h to confgure pin d4 to be an input. applying master enable to gp io pins ( r eg 01h [4] = 1 ) is required. ? e nable trigger delay ( r eg 0 e h [7] = 1), or disable trigger delay ( r eg 0 e h [7] = 0). ? i f using trigger delay, write delay value to r eg 05h [20:0], where r eg 05h [20:0] = number of delayed reference periods. writing r eg 05h [20:0] = 1 for example ensures that the trigger is applied at the instant of the rising edge of the next reference rising edge. d c - 7 ghz f r a ction al- n d ivi d er sweep parameters are defned in the following way: f o i nitial frequency of the synthesizer f f frequency of the synthesizer at the end of the sweep r r eference divider value( r eg 02h [13:0]) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 23 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper stepsize frequency increment step size. i n case of symmetric and u p sweeps, stepsize[47:18] = r eg 12h [29:0], stepsize[17:0] = r eg 13h [17:0]). i n case of asymmetric sweeps, (downsweep stepsize[47:18] = r eg 12h [29:0], down sweep stepsize[17:0] = r eg 13h [17:0]) ?f step frequency step size = 2 xtal l f stepsize r ? ? , l s ize of the d s m (set in r eg 16h [5:0]) t ref period of the divided reference (f pfd ) at the phase detector. t ref = r f xtal n t otal number of frequency step increments in a single sweep. n [47:18] = r eg 14h [29:0], n [17:0] = r eg 15h [17:0] t ramp t otal time of one frequency sweep from f o to f f . t ramp = t ref x n t hen fnal frequency f f is given by: f f = f o + (?f step x n) s etting autoseed ( r eg 0 eh [8] = 1) ensures that different sweeps have identical phase profle. t his is achieved by loading the seed (seed[47:18] = r eg 0ah [29:0], seed[17:0] = r eg 0bh [17:0]) into the phase accumulator at the beginning of each ramp. example: calculate sweep parameters for an asymmetric 2-way sweep from f 0 = 3000 mhz to f f = 3105 mhz with positive t ramp 2 ms, and negative t ramp 4 ms, and positive dwell time = negative dwell time = 2 s, with f pd = 50 mhz, and a 48-bit delta-sigma modulator size. assuming r = 1. 1. calculate the integer and fractional divider values for initial start frequency f 0 ? start nint = reg 05h = 60d ? start nfrac = reg 06h = reg 07h = 0d 2. calculate the number of divided (r = 1) reference periods in the sweep = number of frequency increments n ? nup = 2 ms/(1/50 mhz) = 100000 ? ndown = 4 ms/(1/50 mhz) = 200000 3. calculate stepsize (size of frequency increments) ? stepssize up = abs(f f - f 0 )/nup = abs(3000 mhz - 3105 mhz)/100000 = 1050 hz. then as per t able 6 , reg 12h [29:0] = 0h, reg 13h [17:0] = 1050d = 41ah ? stepsize down = abs(ff - f0)/ndown = abs(3000 mhz - 3105 mhz)/200000 = 525 hz then as per t able 6 , r eg 19h [29:0] = 0h, reg 1ah [17:0] = 1050d = 41ah note that it is possible to have a case where the frequency f f cannot be generated exactly. i n that case it is required to approximate the fnal frequency to f f = f o + (?f step x n ) desired fnal frequency. 4. calculate number of divided (r = 1) reference periods in required dwell time ? up dwell time ( reg 10h [29:0], reg 11h [17:0]) = down dwell time ( reg 06h [29:0], reg 07h [17:0]) = dwell time/ (1/ 50 mhz) = 2 s/(1/50 mhz) = 100. then as per t able 6 , reg 10h [29:0] = reg 06h [29:0] = 0h, and reg 11h [17:0] = reg 07h [17:0] = 100d = 64h. then proceed to confgure the sweep according to the steps outlined in t able 6 . serial port interface t he d c - 7 ghz f r a ction al- n d ivi d er features a four wire serial port for simple communication with the host controller. t ypical serial port operation can be run with sc k at speeds up to 30 mhz. t he details of s p i access for the d c - 7 ghz f r a ction al- n d ivi d er is provided in the following sections. n ote that the re ad operation below is always preceded by a w rite operation to r egister 0 to defne the register to be queried. also note that every re ad cycle is also a w rite cycle in that data sent to the s p i while reading the data will also be stored by the d c - 7 ghz f r a ction al- n d ivi d er when sen b goes high. i f this is not desired then it is suggested to write to r egister 0 during the re ad operation so that the status of the device will be unaffected. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 24 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper power on reset and soft reset t he d c - 7 ghz f r a ction al- n d ivi d er has a built in power o n r eset (p or ) and a serial port accessible s oft r eset ( sr ). p or is accomplished when power is cycled for the d c - 7 ghz f r a ction al- n d ivi d er while sr is accomplished via the s p i by writing r eg 00h = 80h, followed by writing r eg 00h =00h. all chip registers will be reset to default states approximately 250 us after power up. serial port write operation t he host changes the data on the falling edge of sc k and the d c - 7 ghz f r a ction al- n d ivi d er reads the data on the rising edge. a typical w rite cycle is shown in figure 28 . i t is 40 clock cycles long. 1. t he host both asserts sen b (active low s erial port e nable) and places the m s b of the data on s d i followed by a rising edge on sc k. 2. d c - 7 ghz f r a ction al- n d ivi d er reads s d i (the m s b) on the 1st rising edge of sc k after sen b. 3. d c - 7 ghz f r a ction al- n d ivi d er registers the data bits, d29:d0, in the next 29 rising edges of sc k (total of 30 data bits). 4. host places the 5 register address bits, a6:a0, on the next 7 falling edges of sc k (m s b to l s b) while the d c - 7 ghz f r a ction al- n d ivi d er reads the address bits on the corresponding rising edge of sc k. 5. host places the 3 chip address bits, c a2: c a0=[110], on the next 3 falling edges of sc k (m s b to l s b). n ote the d c - 7 ghz f r a ction al- n d ivi d er chip address is fxed as 7d or 111b. 6. sen b goes from low to high after the 40th rising edge of sc k. t his completes the w rite cycle. 7. d c - 7 ghz f r a ction al- n d ivi d er also exports data back on the s d o line. for details see the section on re ad operation. serial port read operation t he s p i can read from the internal registers in the chip. t he data is available on s d o pin. t his pin itself is tri-stated when the device is not being addressed. however when the device is active and has been addressed by the s p i master, the d c - 7 ghz f r a ction al- n d ivi d er controls the s d o pin and exports data on this pin during the next s p i cycle. d c - 7 ghz f r a ction al- n d ivi d er changes the data to the host on the rising edge of sc k and the host reads the data from d c - 7 ghz f r a ction al- n d ivi d er on the falling edge. a typical re ad cycle is shown in figure 28 . r ead cycle is 40 clock cycles long. t o specifcally read a register, the address of that register must be written to dedicated reg 0h . t his requires two full cycles, one to write the required address, and a 2nd to retrieve the data. a read cycle can then be initiated as follows; 1. t he host asserts sen b (active low s erial port e nable) followed by a rising edge sc k. 2. d c - 7 ghz f r a ction al- n d ivi d er reads s d i (the m s b) on the 1 st rising edge of sc k after sen b. 3. d c - 7 ghz f r a ction al- n d ivi d er registers the data bits in the next 29 rising edges of sc k (total of 30 data bits). the lsbs of the data bits represent the address of the register that is intended to be read. 4. host places the 7 register address bits on the next7 falling edges of sc k (m s b to l s b) while the d c - 7 ghz f r a ction al- n d ivi d er reads the address bits on the corresponding rising edge of sc k. for a read operation this is 0000000. 5. host places the 3 chip address bits [111] on the next 3 falling edges of sc k (m s b to l s b). 6. sen b goes from low to high after the 40th rising edge of sc k. t his completes the frst portion of the re ad cycle. 7. t he host asserts sen b (active low s erial port e nable) followed by a rising edge sc k. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 25 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper 8. d c - 7 ghz f r a ction al- n d ivi d er places the 30 data bits, 7 address bits, and 3 chip id bits, on the s d o , on each rising edge of the sc k, commencing with the frst rising edge beginning with m s b. 9. t he host de-asserts sen b (i.e. sets sen b high) after reading the 40 bits from the s d o output. t he 40 bits consists of 30 data bits, 7 address bits, and the 3 chip id bits. t his completes the read cycle. n ote that the data sent to the d c - 7 ghz f r a ction al- n d ivi d er s p i during this portion of the re ad operation is stored in the s p i when sen b is de-asserted. i t is recommended that during the second phase of the re ad operation that r eg 00h is addressed with either the same address or the address of another register to be read during the next cycle. figure 28. spi timing diagram d v dd = 5 v 10%, g n d = 0 v table 7. main spi timing characteristics parameter c onditions min t yp max u nits t 1 s d i to sc k s etup t ime 8 nsec t 2 s d i to sc k hold t ime 8 nsec t 3 sc k high duration [1] 10 nsec t 4 sc k low duration 10 nsec t 5 sen b low duration 20 nsec t 6 sen b high duration 20 nsec t 7 sc k to sen b [2] 8 nsec t 8 sc k to s d o out [3] 8 nsec [1] t he s p i is relatively insensitive to the duty cycle of sc k. [2] sen b must rise after the 32 nd falling edge of sc k but before the next rising sc k edge. i f sc k is shared amongst several devices this timing must be respected. [3] t ypical load to s d o is 10 pf, maximum 20 pf for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 26 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper register map table 8. reg 00h chip id, soft reset, read register bit type name w deflt description [6:0] r /w r ead r egister address 7 0 address of the register to be read in the next cycle. [7] r /w s oft r eset 1 0 s oft r eset. writing 1 generates soft reset. r esets all the digital and registers to default states. writing 0 resumes normal chip operation. [31:8] r /w c hip i d 24 97330h part n umber, description. r ead reg00h returns chip i d. table 9. reg 01h - settings register bit type name w deflt description [0] r /w vco buffer e nable 1 1 e nables vco input r f buffer. [1] r /w r eserved 1 1 write 0 to this bit. [2] r /w a u x s p i e nable 1 1 e nables auxiliary s p i . [3] r /w s igma delta e nable 1 1 e nables s igma delta function. [4] r /w gp io e nable 1 1 e nables output from all gp io pins. [5] r /w r f divider e nable 1 1 e nables r f divider. [6] r /w o utput buffer e nable 1 1 e nables divider o utput driver. [7] r /w bias e nable 1 1 e nables bias generator for all blocks. [8] r /w p sc lk to digital e nable 1 1 e nable prescaler clock going to digital counters. [9] r /w u nused 1 1 table 10. reg 02h r-divider register bit type name w deflt description [13:0] r /w r divider r atio 14 1h local value for reference division ratio. auxiliary spi registers t he following two registers defne the communication through the a u x s p i . i f the a u x s p i is enabled ( r eg 04h [4] = 0), writes to a u x s p i are executed via r eg 03h . t he auxiliary device address is expected in r eg 04h [2:0]. i f d c - 7 ghz f r a ction al- n d ivi d er is working as a standalone frequency divider the a u x s p i clock is expected on the d ns a t pin, and r eg 04h [15] must be set to 1. i t is recommended to disable a u x s p i when not used. table 11. reg 03h aux. vco data register bit type name w deflt description [3:0] r /w a u x s p i r egister address 4 0h 4-bit r egister address for the auxiliary device s p i . [12:4] r /w a u x sp i data 9 000h 9-bit long r egister data for the auxiliary device s p i . for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 27 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper table 12. reg 04h - aux. vco settings register bit type name w deflt description [2:0] r /w auxiliary device address 3 000h c hip address used by a u x s p i . [3] r /w divide c lock by 4 for a u x s p i 1 0 0 = u se x t al for a u x s p i clock. 1 = u se x t al divided by 4 for a u x s p i clock. [4] r /w s tart a u xs p i 1 0 0 = s tart a u x s p i when data is written to r eg03h. 1 = reserved. [7:5] r /w r eserved 3 4h [9:8] r /w r eserved 2 2h [13:10] r /w r eserved 4 8h [14] r /w r eserved 1 0 [15] r /w keep xtal gate o pen 1 0 when 1, keeps the x t al gate open to get x t al from the companion pfd/ c p chip hm c 984lp4 e . [18:16] r /w r eserved 3 0h table 13. reg 05h integer set-point, trigger delay register bit type name w deflt description [19:0] r /w i nteger division r atio 20 200d s igma-delta modulator integer set point. s pecifes the integer part of the division ratio for the r f divider in fractional mode or the integer division ration in integer mode. r amp t rigger delay also used as delay counter for hardware ramp trigger (pin d4) in ramp mode. t his value is valid when r eg 0 e h [11] = 1. table 14. reg 06h fractional set-point, down dwell register (msb) bit type name w deflt description [29:0] r /w fractional division r atio (m s b) 30 0 most signifcant 30 bits to specify fractional set point for s igma- delta modulator. t otal fractional bits are 48. down dwell for asymmetric frequency. r amp (m s b) defnes the m s b portion of the dwell down time in the asymmetric frequency sweep mode, valid when r eg 0 e h [11] =1. table 15. reg 07h fractional set-point, down dwell register (lsb) bit type name w deflt description [17:0] r /w fractional division r atio (l s b) 18 0 least signifcant 18 bits to specify fractional set point for s igma- delta modulator. t otal fractional bit are 48. down dwell for asymmetric frequency. r amp (l s b) defnes the l s b portion of the dwell down time in the asymmetric frequency sweep mode, valid when r eg0 e [11]=1. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 28 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper table 16. reg 08h gpio confguration register bit type name w deflt description [3:0] r /w gp o o utput s elect 4 0h s elects exported output signals to gp io pins. s ee t able 5 for details. master enable for gp io r eg 01h [4] = 1 is required. . [8:4] r /w gp o s tatic t est v alue 5 00000b s tatic gp io test signals for output (d4,d3,d2,d1,d0). writing these value and reading them back test the gp io functionality. master enable for gp io r eg 01h [4] = 1 is required. . [13:9] r /w gp o pin e nable 5 11111b i ndependent gp io pin enables. r eg08[13] = 0 - d4 input r eg08[13] = 1 - d4 output r eg08[12] = 0, d3 input r eg08[12] =1, d3 output r eg08[11] = 0, d2 input r eg08[11] = 1, d2 output r eg08[10] = 0, d1 input r eg08[10] = 1, d1 output r eg08[9] = 0, d0 input r eg08[9] = 1, d0 output master enable for gp io r eg 01h [4] = 1 is required. table 17. reg 09h companion chip address local register bit type name w deflt description [2:0] r /w c ounterpart hm c 984lp4 e c hip address 3 2h c hip address of the companion chip hm c 984lp4 e. table 18. reg 0ah sigma delta modulator seed msb register bit type name w deflt description [29:0] r /w s eed m s b 30 4241h most signifcant bits of the s eed for the 1st accumulator in s igma-delta modulator. table 19. reg 0bh sigma delta modulator seed lsb register bit type name w deflt description [17:0] r /w s eed l s b 18 10081h least signifcant bits of the s eed for the 1st accumulator in s igma-delta modulator. table 20. reg 0ch ramp nstep down msb register bit type name w deflt description [29:0] r /w down r amp n umber of s teps (m s b) 30 0h most signifcant bits of the number of steps for the frequency ramp in down direction in sweep mode. table 21. reg 0dh ramp nstep down lsb register bit type name w deflt description [17:0] r /w down r amp n umber of s teps (l s b) 18 0h least signifcant bits of the number of steps for the frequency ramp in down direction in sweep mode. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 29 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper table 22. reg 0eh sigma delta modulator confguration register bit type name w deflt description [1:0] r /w s d modulator t ype 2 11b d s m t ype. 00 = ma s h1 - r eserved 01 = ma s h11 - r eserved 10 = ma s h111 - delta s igma modulator mode b 11 - delta s igma modulator mode a [2] r /w r amp auto r epeat c ontrol from s pi 1 0 r ecommended to write 1 to this bit in ramp mode. when this bit is 1, the ramp will repeat itself if ramp_auto_repeat_on/off_from_ spi is 1 at the end of the each sweep. [3] r /w r amp auto r epeat c ontrol from s pi o n/ o ff 1 0 r amp will automatically repeat itself if this bit is 1 and bit 2 is also set to 1. [6:4] r /w i nteger path delay 3 111 delay through the integer signal path to compensate for the fractional path. 000 = no delay. 110 = 6 clock cycles delay. 111 = auto m at i c. [7] r /w r amp s tart delay e nable 1 0 delay the start of sweep as defned in r eg 05h [8] r /w autoseed mode e nable 1 1 r eseed when changing the frac setpoint. [9] r /w phase s tep 1 0 1 = e nable phase s tep feature. autoseed mode must be disabled for phase s tep ( r eg 0 e h [8] = 0. s eed r eg ah & r eg bh set the phase advance/retard in 2s complement formate. phase s tep takes effect when r eg 0ah is written. e ach time registers are written phase will advance/retard by the amount specifed. [10] r /w maintain d s m s tate e nable 1 0 maintain d s m state within the same integer boundary. [11] r /w r amp mode e nable 1 0 puts d s m in frequency sweeper (ramp) mode. [12] r /w r amp s tart from s p i 1 0 s tart ramp signal from s p i . [13] r /w s tart r amp from e xt. t rigger 1 0 allow external trigger to manipulate ramp. [14] r /w bypass all 1 0 bypass delta s igma modulator. place synthesizer in i nteger mode without disabling the d s m. [18:15] r /w cs p s tep s ize 4 1111b c ycle s lip prevention ( cs p) step size. i n a pll confguration with the hm c 984lp4 e one step is equivalent to one divided vco cycle, and step size is the number of vco cycles. [19] r /w e xternal d s m s equence e nable 1 0 u se external d s m sequence imported through gp io port. [20] r /w u se falling e dge of d s m c lock for e xternal s equence 1 0 u se falling edge of s d clock to get the external sequence. [21] r /w lock using e xternal t rigger pin 1 0 allow external trigger to start locking process. writing to the i nteger or fractional division ratio registers does not have any effect when this bit is set to 1. pll will lock only when external trigger goes high. [22] r /w s ymmetrical r amp mode 1 1 u se symmetric frequency sweeping for up and down directions otherwise d n parameters are taken from r egisters r eg 0 ch , r eg 0dh , r eg 19h and r eg 1ah for asymmetric mode. [23] r /w i nteger mode lock s trobe 1 0 r e-lock when integer set-point r eg 06h is updated. [24] r /w s inglestep r amp mode e nable 1 0 s ingle-step the ramp. e ach step of the ramp must be popped by strobe (either s p i or hardware pin). [25] r /w s ingle direction r amp mode e nable 1 0 s ingle direction mode for ramp (ramp one way, pop to base the other way). [26] r /w r amp s tart direction 1 1 s tarting direction of ramp. i t is only loaded while rampmode = 0. 1 = positive 0 = n egative for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 30 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper [27] r /w u se e xternal c lock for d s m 1 0 1 = u se external clock from gp io pin to clock d s m. [28] r /w r eserved 1 0 [29] r /w u se x16 cs p s tep 1 0 1 = i ncrease the cs p step size given in bits [18:15] by a factor of 16. table 23. reg 0fh vco divider confguration register bit type name w deflt description [0] r /w i ncrease divider pulse width to d s m 1 0 i ncrease the width of the clock pulse going to d s m (available only when division ratio > 64). [1] r /w i ncrease divider pulsewidth to pfd 1 1 i ncrease pulse width (low duration) of the clock going to pfd. [4:2] r /w o utput buffer c urrent s elect 2 011b s ets current for divider output buffer. helps to control voltage swing for various impedance options. 000 = 5ma 001 = 7.5ma 010 = 10ma 011 = 12.5ma 100 = 10ma 101 = 12.5ma 110 = 15ma 111 = 17. 5m a [5] r /w r eset r f divider 1 0 r esets the r f divider. [8:6] r /w divider r esynch bias s elect 3 011b bias current setting for divider resync. default value recommended. [11:9] r /w r f buffer bias s elect 3 001b bias current setting for input r f buffer. default value recommended. [14:12] r /w divider pulsewidth s elect 3 011b divider output pulse width control. 000 = 5 vco cycles. 001 = 13 vco cycles. 010 = 21 vco cycles. 011 = 29 vco cycles. 100 = 37 vco cycles. 101 = 45 vco cycles. 110 = 53 vco cycles. 111 = 61 vco cycles. table 24. reg 10h ramp dwell symmetrical or up msb register bit type name w deflt description [29:0] r /w s ymmetric r amp dwell (m s b) 30 0 r epresents m s bs for ramp dwell time in up and down directions for symmetric frequency sweep mode. i n asymmetric mode it represents the up dwell time only. table 25. reg 11h ramp dwell symmetrical or up lsb register bit type name w deflt description [17:0] r /w s ymmetric r amp dwell (l s b) 18 0 r epresents l s bs for ramp dwell time in up and down directions for symmetric frequency sweep mode. i n asymmetric mode it represents the up dwell time only. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 31 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper table 26. reg 12h ramp step size symmetrical or up msb register bit type name w deflt description [29:0] r /w s ymmetric r amp s tep s ize (m s b) 30 0 r epresents the m s b for ramp step size in up and down directions for symmetric frequency sweep mode. i n asymmetric mode it represents the up step size only. table 27. reg 13h ramp step size symmetrical or up lsb register bit type name w deflt description [17:0] r /w s ymmetric r amp s tep s ize (l s b) 18 0 r epresents the l s b for ramp step size in up and down directions for symmetric frequency sweep mode. i n asymmetric mode it represents the up step size only. table 28. reg 14h ramp nstep symmetrical or up msb register bit type name w deflt description [29:0] r /w s ymmetric r amp n umber of s teps (ms b) 30 0 r epresents the m s b of the number of steps for the frequency ramp in up and down directions in symmetric frequency sweep mode. i n asymmetric mode it represents the number of steps in up direction only. table 29. reg 15h ramp nstep symmetrical or up lsb register bit type name w deflt description [17:0] r /w s ymmetric r amp n umber of s teps (l s b) 18 0 r epresents the l s b of the number of steps for the frequency ramp in up and down directions in symmetric frequency sweep mode. i n asymmetric mode it represents the number of steps in up direction only. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
frequency divi d ers & detectors - s m t 32 hmc983lp5e v 0 2.0112 dc - 7 ghz fractional-n divider and frequency sweeper table 30. reg 16h dsm confguration register bit type name w deflt description [1:0] r /w d s m 1st accumulator s ize 2 00b d s m 1st accumulator width. 00 = 48 bits 01 = 32 bits 10 = 24 bits 11 = 16 bits [3:2] r /w d s m 2nd accumulator s ize 2 00b d s m 2nd accumulator width. 00 = 48 bits 01 = 32 bits 10 = 24 bits 11 = 16 bits [5:4] r /w d s m 3rd accumulator s ize 2 00b d s m 3rd accumulator width. 00 = 48 bits 01 = 32 bits 10 = 24 bits 11 = 16 bits [8:6] r /w disable frac. r egister c lock 3 000b c lock gates for the 3 accumulators (fractional part), 1 disables the clock. [11:9] r /w disable i nteger r egister c lock 3 000b c lock gates for the 3 accumulators (integer part), 1 disables the clock. [12] r /w disable d s m mode a c lock 1 0 1 = disable delta s igma modulator mode a c lock [13] r /w disable d s m mode b c lock 1 0 1 = disable delta s igma modulator mode b c lock [14] r /w r eserved 1 0 [15] r /w disable i nteger path c lock 1 0 1 = disables i nteger path c lock [16] r /w disable i nput buffer c lock 1 0 1 = disables i nput buffer c lock [17] r /w disable o utput buffer c lock 1 0 1 = disables o utput buffer c lock [18] r /w r eserved 1 0 [19] r /w r eserved 1 0 table 31. reg 17h this register does not exist bit type name w deflt description t his r egister does not exist table 32. reg 19h ramp down step size msb register bit type name w deflt description [29:0] r /w r amp s tep down m s b. 30 0 r epresents m s bs to defne the step size for the ramp in down direction in ramp mode. table 33. reg 1ah ramp down step size lsb register bit type name w deflt description [17:0] r /w r amp s tep down l s b. 18 0 r epresents l s bs to defne the step size for the ramp in down direction in ramp mode. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com

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